IBIS Macromodel Task Group Meeting date: 09 April 2024 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark Wei-hsing Huang Aurora System: Dian Yang Raj Raghuram Cadence Design Systems: * Ambrish Varma Jared James Dassault Systemes: Longfei Bai Google: Hanfeng Wang GaWon Kim Intel: * Michael Mirmak Kinger Cai Chi-te Chen Liwei Zhao Alaeddin Aydiner Keysight Technologies: Fangyi Rao Majid Ahadi Dolatsara Stephen Slater Ming Yan Rui Yang Marvell: Steve Parker Mathworks (SiSoft): Walter Katz Graham Kus Micron Technology: Justin Butterfield Missouri S&T: Chulsoon Hwang Yifan Ding Zhiping Yang Rivos: Yansheng Wang SAE ITC: Michael McNair Siemens EDA (Mentor): * Arpad Muranyi * Randy Wolff Teraspeed Labs: [Bob Ross] Zuken USA: Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - Arpad noted that the meeting scheduled for April 2nd had been cancelled because of limited attendee availability. ------------- Review of ARs: Michael: Submit draft4 of the Block Clarification proposal to IBIS Open Forum. - Done. It was submitted as BIRD231. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the March 26th meeting. Michael moved to approve the minutes. Ambrish seconded the motion. There were no objections. -------------- New Discussion: Fixing [Clock Pins]: Michael briefly reviewed the topic and summarized discussions from previous meetings. He said BIRD208 had introduced [Clock Pins] into IBIS 7.1 back in 2021. He said the goal of [Clock Pins] had been to associate clock pins with their clocked (e.g., data) pins. It could establish the association, but it did not define the exact relationship. He said [Clock Pins] works well for DRAMs, but it was discovered that it does not easily support DDR controllers. A controller might have multiple modes. It might be configurable to support 4 data lines (nibble) or 8 data lines (byte) from a given clock line, for example. [Clock Pins] does not easily support such a configurable device, as the pin associations are defined once when the .ibs file is created. It does not easily support switching between two different sets of associations, i.e., two different modes. Michael said that we need something analogous to a [Model Selector] to support configurable devices such as DDR controllers. Michael proposed a new solution that would repurposes the third column (the relationship sub-param) in the [Clock Pins] keyword. The third column could contain a value indicating a grouping, which could serve as a clock selector. Michael reviewed a [Clock Pins] example illustrating the nibble and byte cases in the same [Clock Pins] keyword using different "x4" and "x8" groupings. [Clock Pins] clocked_pins relationship A1 B1 x4 | Pins B1, B2, B3, B4 use clock information from A1 A1 B2 x4 | and can be organized as x4 A1 B3 x4 A1 B4 x4 A2 B5 x4 | Pins B5, B6, B7, B8 use clock information from A2 A2 B6 x4 | and can be organized as x4 A2 B7 x4 A2 B8 x4 | A1 B1 x8 | Pins B1, B2, B3, B4 A1 B2 x8 | B5, B6, B7, B8 use clock information from A1 A1 B3 x8 | and can be organized as x8 A1 B4 x8 A1 B5 x8 A1 B6 x8 A1 B7 x8 A1 B8 x8 Michael said the changes required would be to lift the current (7.2) restriction that says only "Unspecified" is allowed in the relationship column, and remove the following sentence: The structure of [Clock Pins] assumes that the clocking relationships cannot be redefined dynamically for the given [Component] (for example, the number of data pins supported by any one clock pin is fixed). Arpad said we have to be careful about the term "dynamically". He asked whether we explicitly state that you can't change the selection during simulation. He said that for [Model Selector] we don't seem to explicitly state that it can't be changed during the simulation, but it is strongly implied by this sentence from the Usage Rules: The purpose of the descriptions is to aid the user of the EDA tool in making intelligent buffer mode selections and it can be used by the EDA tool in a user interface dialog box as the basis of an interactive buffer selection mechanism. Michael agreed that the issue is the meaning of "dynamic". He said that in this [Clock Pins] language he thought of static as meaning that the pin associations were defined at the time of model creation and can't be changed. By "dynamic" he meant that we would be able to handle a mode of operation change, which might occur with a reboot or configuration change or firmware change. The clock selector concept would allow us to do this. Michael said the intent was never to support changing pin relationships in the middle of a simulation. Michael noted that he would be unable to attend the next two meetings. Given that the agenda was sparse aside from Michael's proposals, the group decided to cancel the meetings scheduled for April 16th and April 23rd. - Michael: Motion to adjourn. - Curtis: Second. - Arpad: Thank you all for joining. New ARs: None. ------------- Next meeting: 30 April 2024 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives